The present invention relates to the field of signal conversion and, more particularly, to circuits to scale signal voltage.
In a number of situations, a signal voltage will need to be reduced in order to couple the signal to the next circuit. Although a voltage divider network or circuit can provide a requisite step down in the voltage level of the signal, in certain applications such voltage divider reduction may not provide the adequate performance needed for the driven circuit. When the driven circuit operates at a substantially lower voltage then the driving circuit, a simple voltage divider reduction could introduce significant jitter and skew at the input of the driven circuit. For example, when the signal is a clocking signal and the driven circuit is a processor operating at a sufficiently fast speed, performance problems could be encountered if a reduction of the clocking signal is needed at the input of the processor. State of the art processors of today operate at input clock frequencies of 100 MHz or higher and these clock frequencies are multiplied within the processor chip itself. At these higher frequencies of operation, the processors may operate near or below 1.0 volt level. This is especially true of processors utilized for mobile applications where lower supply voltage for the processor core is imperative in order to conserve battery life.
Although the processor technology has developed to improve the performance of the processors, clock generators have not improved upon the technology to produce lower voltage clocking circuitry. Part of the reason stems from the fact that lower voltage circuits typically are more expensive to manufacture than circuitry utilizing higher supply voltages. Accordingly, many clock vendors continue to produce clock generator chips operating at the supply voltages around 3.3 volts. In order to utilize a 3.3 volt clocking signal to drive a processor operating at a supply voltage of around 1.0 volt or below, the clock signal will need to be reduced to a fraction of its output level in order to drive the processor. Since rail-to-rail transition is much smaller for the reduced voltage signal, jitter at the input is more noticeable during the transition. Although it is possible to increase the slew rate by implementing a large device, a significant increase in the slew rate will most likely introduce undesirable electromagnetic interference (EMI) and in some instances this EMI level is beyond standards permitted for the computing devices at low voltage, it is difficult to increase the slew rate.
As a further problem, some form of over-voltage protection is typically desirable in order to prevent an accidental increase in the input voltage which could damage the processor. Additionally, if the supply operating voltage of the processor drops below a volt (for example, to 0.9 volts) the processor supply voltage is approaching the threshold voltage of the clocking circuit, so that adequate signal transition may be impaired due to the closeness of the supply voltage of the processor to the threshold turn on voltage of the circuitry of the clock generator. Accordingly, for various reasons noted, a solution is needed, especially for lower supply voltage devices, such as the example processor described above.